This present invention relates to a phase-locked loop (PLL); more particularly, the present invention relates to a PLL capable of compensating the VCO tuning sensitivity by adjusting the phase detector gain according to the VCO tuning sensitivity so as to minimize the variation of the loop bandwidth of the PLL.
In communication systems, the phase-locked loop (PLL) is a device used for generating an output signal having a specific phase and a specific frequency. In order to achieve this goal, it is desired that the variation of the loop bandwidth (W) of the PLL could be minimized as much as possible.
Referring to FIG. 1, FIG. 1 is a system block diagram of a conventional PLL 10. The conventional PLL 10 comprises a phase detector 12, a loop filter 14, a voltage controlled oscillator (VCO) 16, and a frequency converter 18. The phase detector 12 is used for receiving an input signal (FI) and a reference signal (FR) and for comparing the phases of the input signal (FI) and a reference signal (FR), so as to obtain a phase difference signal (SP) representing the phase difference (Δ) between these two input signals FI and FR. Receiving and filtering the phase difference signal (SP), the loop filter 14 outputs a frequency controlled signal (Vt) to the VCO 16. The VCO 16 generates an output signal (fPLL) as the output of the PLL 10. The frequency converter 18 receives the output signal (fPLL), down-converts the output signal (fPLL), and generates the reference signal (fR) that is thus fed to the phase detector 12. As is well known in the art, a loop bandwidth (W) of the PLL is proportional to the square root of the product of a VCO gain (KVCO) and a phase detector gain (KPD), wherein the VCO gain (KVCO) represents a ratio of the variation of the output signal (fPLL) to the variation of the frequency controlled signal (Vt), and the phase detector gain (KPD) represents a ratio of the phase difference signal (Sp) to the phase difference (Δ). The VCO gain (KVCO) is also referred as the tuning sensitivity.
Referring to FIG. 2, FIG. 3, and FIG. 4, FIG. 2 is a graph showing the relationship between the VCO gain (KVCO) and the frequency controlled signal (Vt); FIG. 3 is a graph showing the relationship between the phase detector gain (KPD) and the frequency controlled signal (Vt); FIG. 4 is a graph showing the relationship between the loop bandwidth (W) and the frequency controlled signal (Vt). Traditional VCO 16 is well developed to achieve a good linearity of the VCO gain (KVCO), which means the VCO gain (KVCO) substantially remains at a specific value within the operating range of the frequency controlled signal (Vt). However, when the PLL system is integrated into an integrated circuit (IC), the linearity of the VCO gain (KVCO) becomes a seriously challenging issue. As shown in FIG. 2, the VCO gain (KVCO) will have substantially different value for different frequency controlled signal (Vt). Though the phase detector gain (KPD) might have perfect linearity (as shown in FIG. 3), the corresponding loop bandwidth (W) will have a undesired variation due to the poor linearity of the VCO gain (KVCO). As shown in FIG. 4, the variation of the loop bandwidth (W) within the operating range of the frequency controlled signal (Vt) becomes too large to be acceptable.
Referring to FIG. 5, FIG. 5 is a system block diagram of another conventional PLL 20, disclosed in U.S. Patent Publication NO. 2002/0039050A1. Conventional PLL 20 comprises a VCO 25, a frequency divider 29, a phase detector 22, a charge pump 23, a loop filter 24, and a gain controller 26. The VCO 25 is used for receiving a frequency controlled signal (Vt), and for generating an output signal (Fout) correspondingly. The frequency divider 29 is used for dividing the output signal (Fout) according to a selected divisor and for generating a first feedback signal (Ffb). The phase detector 22 is a digital phase detector for detecting the phase difference between a reference signal (Fref) and the first feedback signal (Ffb) and for outputting a phase difference signal (Sp). The charge pump 23 is used for receiving the phase difference signal (Sp) and for generating a current signal (Ifc), wherein a charge pump gain (KC) of the charge pump 23 can be adjusted by a gain controlled signal (Sgc). The loop filter 24 is used for filtering the current signal (Ifc) outputted from the charge pump 23 and for generating the frequency controlled signal (Vt). The frequency controlled signal (Vt) is further transmitted to a high impedance buffered amplifier/filter 27, and then a second feedback signal (Vfb) is obtained. The gain controller 26 is used for receiving the second feedback signal (Vfb). After the second feedback signal (Vfb) is converted from analog format to digital format via an analog/digital converter 28 comprised in the gain controller 26, the second feedback signal (Vfb) in digital format is taken as an index for looking into a look-up table (not shown) built in the gain controller 26 to obtain the gain controlled signal (Sgc) for adjusting the charge pump gain (KC).
As is well known in the art, the loop bandwidth (W) is proportional to the square root of the product of the VCO gain (KVCO) and the charge pump gain (Kc), the conventional PLL 20 minimize the variation of the loop bandwidth (W) by adjusting the charge pump gain (Kc). However, conventional PLL 20 disclosed in U.S. Patent Publication NO. 2002/0039050A1 can only be applied for the situation when the phase detector in the PLL is a digital one, which would have an associated charge pump, rather than an analog one, which would not have a charge pump. Therefore, it is still a problem how to compensate the loop bandwidth of a PLL having an analog phase detector in an IC.